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Anna University
Question Paper Code : 25059
B.E/B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2018.
Third Semester
Computer Science and Engineering
CS 8351 Digital Principles and System Design
( Common to Information Technology / Electronics and Telecommunication Engineering )
( Regulation 2017 )
Question Paper Code : 25059
B.E/B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2018.
Third Semester
Computer Science and Engineering
CS 8351 Digital Principles and System Design
( Common to Information Technology / Electronics and Telecommunication Engineering )
( Regulation 2017 )
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CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN
OBJECTIVES:
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 12
Number Systems – Arithmetic Operations – Binary Codes- Boolean Algebra and Logic Gates – Theorems and Properties of Boolean Algebra – Boolean Functions – Canonical and Standard Forms – Simplification of Boolean Functions using Karnaugh Map – Logic Gates – NAND and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 12
Combinational Circuits – Analysis and Design Procedures – Binary Adder-Subtractor – Decimal Adder – Binary Multiplier – Magnitude Comparator – Decoders – Encoders – Multiplexers – Introduction to HDL – HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 12
Sequential Circuits – Storage Elements: Latches , Flip-Flops – Analysis of Clocked Sequential Circuits – State Reduction and Assignment – Design Procedure – Registers and Counters – HDL Models of Sequential Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 12
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 12
RAM – Memory Decoding – Error Detection and Correction – ROM – Programmable Logic Array – Programmable Array Logic – Sequential Programmable Devices. TOTAL : 60 PERIODS
OUTCOMES:
On Completion of the course, the students should be able to:
Simplify Boolean functions using KMap
Design and Analyze Combinational and Sequential Circuits
Implement designs using Programmable Logic Devices
Write HDL code for combinational and Sequential Circuits
TEXT BOOK:
1. M. Morris R. Mano, Michael D. Ciletti, ―Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog‖, 6th Edition, Pearson Education, 2017.
REFERENCES
1. G. K. Kharate, Digital Electronics, Oxford University Press, 2010
2. John F. Wakerly, Digital Design Principles and Practices, Fifth Edition, Pearson Education, 2017.
3. Charles H. Roth Jr, Larry L. Kinney, Fundamentals of Logic Design, Sixth Edition, CENGAGE Learning, 2013
4. Donald D. Givone, Digital Principles and Design‖, Tata Mc Graw Hill, 2003.
OBJECTIVES:
• To design digital circuits using simplified Boolean functions
• To analyze and design combinational circuits
• To analyze and design synchronous and asynchronous sequential circuits
• To understand Programmable Logic Devices
• To write HDL code for combinational and sequential circuits
• To analyze and design combinational circuits
• To analyze and design synchronous and asynchronous sequential circuits
• To understand Programmable Logic Devices
• To write HDL code for combinational and sequential circuits
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 12
Number Systems – Arithmetic Operations – Binary Codes- Boolean Algebra and Logic Gates – Theorems and Properties of Boolean Algebra – Boolean Functions – Canonical and Standard Forms – Simplification of Boolean Functions using Karnaugh Map – Logic Gates – NAND and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 12
Combinational Circuits – Analysis and Design Procedures – Binary Adder-Subtractor – Decimal Adder – Binary Multiplier – Magnitude Comparator – Decoders – Encoders – Multiplexers – Introduction to HDL – HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 12
Sequential Circuits – Storage Elements: Latches , Flip-Flops – Analysis of Clocked Sequential Circuits – State Reduction and Assignment – Design Procedure – Registers and Counters – HDL Models of Sequential Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 12
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 12
RAM – Memory Decoding – Error Detection and Correction – ROM – Programmable Logic Array – Programmable Array Logic – Sequential Programmable Devices. TOTAL : 60 PERIODS
OUTCOMES:
On Completion of the course, the students should be able to:
Simplify Boolean functions using KMap
Design and Analyze Combinational and Sequential Circuits
Implement designs using Programmable Logic Devices
Write HDL code for combinational and Sequential Circuits
TEXT BOOK:
1. M. Morris R. Mano, Michael D. Ciletti, ―Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog‖, 6th Edition, Pearson Education, 2017.
REFERENCES
1. G. K. Kharate, Digital Electronics, Oxford University Press, 2010
2. John F. Wakerly, Digital Design Principles and Practices, Fifth Edition, Pearson Education, 2017.
3. Charles H. Roth Jr, Larry L. Kinney, Fundamentals of Logic Design, Sixth Edition, CENGAGE Learning, 2013
4. Donald D. Givone, Digital Principles and Design‖, Tata Mc Graw Hill, 2003.
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