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Anna University
Question Paper Code : 20356
B.E/B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2018.
Second Semester
Computer Science and Engineering
CS 6201 Digital Principle And System Design
( Common to Information Technology )
( Regulation 2013 )
Question Paper Code : 20356
B.E/B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2018.
Second Semester
Computer Science and Engineering
CS 6201 Digital Principle And System Design
( Common to Information Technology )
( Regulation 2013 )
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CS6201 Digital Principle And System Design syllabus
OBJECTIVES:
The student should be made to:
- Learn the various number systems.
- Learn Boolean Algebra
- Understand the various logic gates.
- Be familiar with various combinational circuits.
- Be familiar with designing synchronous and asynchronous sequential circuits.
- Be exposed to designing using PLD
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9
Review of Number Systems – Arithmetic Operations – Binary Codes – Boolean Algebra and Theorems – Boolean Functions – Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods – Logic Gates – NAND and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 9
Combinational Circuits – Analysis and Design Procedures – Circuits for Arithmetic Operations, Code Conversion – Decoders and Encoders – Multiplexers and Demultiplexers – Introduction to HDL – HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 9
Sequential Circuits – Latches and Flip Flops – Analysis and Design Procedures – State Reduction and State Assignment – Shift Registers – Counters – HDL for Sequential Logic Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 9
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 9
RAM and ROM – Memory Decoding – Error Detection and Correction – Programmable Logic Array – Programmable Array Logic – Sequential Programmable Devices – Application Specific Integrated Circuits.
TOTAL: 45 PERIODS
OUTCOMES:
At the end of this course, the student will be able to:
- Perform arithmetic operations in any number system.
- Simplify the Boolean expression using K-Map and Tabulation techniques.
- Use boolean simplification techniques to design a combinational hardware circuit.
- Design and Analysis of a given digital circuit – combinational and sequential.
- Design using PLD.
TEXT BOOK:
1. Morris Mano M. and Michael D. Ciletti, “Digital Design”, IV Edition, Pearson Education, 2008.
REFERENCES:
1. John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson Education, 2007.
2. Charles H. Roth Jr, “Fundamentals of Logic Design”, Fifth Edition – Jaico Publishing House, Mumbai, 2003.
3. Donald D. Givone, “Digital Principles and Design”, Tata Mcgraw Hill, 2003.
4. Kharate G. K., “Digital Electronics”, Oxford University Press, 2010.
The student should be made to:
- Learn the various number systems.
- Learn Boolean Algebra
- Understand the various logic gates.
- Be familiar with various combinational circuits.
- Be familiar with designing synchronous and asynchronous sequential circuits.
- Be exposed to designing using PLD
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 9
Review of Number Systems – Arithmetic Operations – Binary Codes – Boolean Algebra and Theorems – Boolean Functions – Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods – Logic Gates – NAND and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 9
Combinational Circuits – Analysis and Design Procedures – Circuits for Arithmetic Operations, Code Conversion – Decoders and Encoders – Multiplexers and Demultiplexers – Introduction to HDL – HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 9
Sequential Circuits – Latches and Flip Flops – Analysis and Design Procedures – State Reduction and State Assignment – Shift Registers – Counters – HDL for Sequential Logic Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 9
Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 9
RAM and ROM – Memory Decoding – Error Detection and Correction – Programmable Logic Array – Programmable Array Logic – Sequential Programmable Devices – Application Specific Integrated Circuits.
TOTAL: 45 PERIODS
OUTCOMES:
At the end of this course, the student will be able to:
- Perform arithmetic operations in any number system.
- Simplify the Boolean expression using K-Map and Tabulation techniques.
- Use boolean simplification techniques to design a combinational hardware circuit.
- Design and Analysis of a given digital circuit – combinational and sequential.
- Design using PLD.
TEXT BOOK:
1. Morris Mano M. and Michael D. Ciletti, “Digital Design”, IV Edition, Pearson Education, 2008.
REFERENCES:
1. John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson Education, 2007.
2. Charles H. Roth Jr, “Fundamentals of Logic Design”, Fifth Edition – Jaico Publishing House, Mumbai, 2003.
3. Donald D. Givone, “Digital Principles and Design”, Tata Mcgraw Hill, 2003.
4. Kharate G. K., “Digital Electronics”, Oxford University Press, 2010.
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