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Anna University Question Paper
B.E./B.Tech. DEGREE EXAMINATION, May /June 2014.
Electronics and Communication Engineering
3rd year
6th Semester
EC2354/EC 64/10144 EC704-VLSI DESIGN
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Part A
1. What are the Non ideal IV effects?
2. Discuss any two layout rules.
3. Define transistor sizing problem.
4. What do you mean by design margin?
5. What are synchronizers?
6. State any two criteria for low power logic design?
7. What is the need for testing?
8. What do you mean by text fixtures?
9. What are procedural assignments in verilog?
10. What is the switch level modelling?
Part B
11 a) Discuss CV characteristics and DC transfer characteristics of the CMOS.(16)
Or
b) Briefly discuss about the CMOS process enhancements and layout design rules.(16)
12 )a) Explain the following(16)
1) Device models and device characterizations.
2) Power dissipation in CMOS circuits.
Or
b) 1) Describe the stimulation of circuit interconnects.(8)
2) Write about SPICE based circuit stimulation.(8)
13) a)Explain the methodology of sequential circuit design of latches and flip flops.(16)
Or
b) Briefly discuss about the classification of circuit families and comparison of circuit families.(16)
14) a)Discuss the need for testing and explain about the silicon debugging principles(16)
Or
b) Explain the method of boundary scan test in detail.(16)
15)a)Explain the following in VERILOG with an suitable example(16)
1) Timing controls and conditional statements.
2) Behavioral and gate level modeling.
Or
b) Write the VERILOG code for(16)
1) Parity Encoder.
2) Equality Detector.
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