# Linear Integrated Circuits 4th ND10 EC2254

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010
Fourth Semester
Electronics and Communication Engineering
EC 2254 — LINEAR INTEGRATED CIRCUITS
(Regulation 2008)
(Common to PTEC 2254 – Linear Integrated circuits for B.E. (Part Time) Third
Semester Electronics and Communication Engineering Regulation 2009)

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PART A — (10 × 2 = 20 Marks)

1. Define slew rate and CMRR.
2. Why are active loads preferred than passive loads in the input stage of an operational amplifier?
3. Compare the performance of inverting and non inverting operational amplifier configurations.
4. Why is frequency compensation required in operational amplifier?
5. Draw and write equation of an integrator using an op-amp.
6. What is lock range and capture range of PLL?
8. Define resolution and conversion time of DAC.
9. Sketch the monostable multivibrator circuit diagram using 1C555.
10. What is meant by thermal shutdown applied to voltage regulators?

PART B — (5 × 16 = 80 Marks)

11. (a) (i) Explain the term epitaxy and describe the epitaxial growth process.
(ii) Describe in detail the processing steps involved in the fabrication of monolithic IC. [Marks 16]
Or
(b) Draw the circuit diagram of the output stage of the IC 741 OP AMP and explain its operation with clearly indicating the protection mechanisms indicated. [Marks 16]

12. (a) With relevant circuits, explain the following applications of OPAMP (i) Voltage to current converters
(ii) Multiplier [Marks 16]
Or
(b) (i) Explain the steps involved in the design of a band pass filter using OPAMP.
(ii) Write a note on Schmitt trigger. [Marks 16]

13. (a) Draw the functional block schematic of a NE565 PLL and explain the roles of the low pass filter and VCO. Derive the expression for the capture range and lock in range of the PLL. [Marks 16]
Or
(b) With suitable block diagram, explain the operation of 566 voltage controlled oscillator. Also derive an expression for the frequency of the output waveform generated. [Marks 16]

14. (a) Describe the operation of dual slope and successive approximation type ADC. What are the advantages of dual slope ADC? [Marks 16]
Or
(b) (i) Explain voltage mode and current mode operations of R-2R ladder type DAC.
(ii) Discuss the operation of sample and hold circuit with circuit diagram. [Marks 16]

15. (a) (i) How can the current drive capability be increased while using three terminal voltage regulators?
(ii) Design an adjustable voltage regulator circuit using LM317 for the following specifications :
Input dc voltage = l3.5 V
Output DC voltage = 5 to 9 V
Load current (maximum) =1 A [Marks 16]
Or
(b) Describe the working of IC723 voltage regulator and explain the importance of current limiting techniques. [Marks 16]