Quick Links
| University Papers | University Syllabus | Entrance Exam |
| PSU Papers | Bank Papers | Placement Papers |
| VTU | Anna Univerity Syllabus | Anna Univerity Papers |
B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011
Sixth Semester
Computer Science and Engineering
CS 2354 - ADVANCED COMPUTER ARCHITECTURE
(Regulation 2008)
University Papers | Syllabus | Entrance Exam | Govt & PSU Papers | Bank Papers
Programming Questions | Travel Tips | Mobile Review | Placement Papers
ANNA UNIVERSITY SYLLABUS: CLICK HERE
ANNA UNIVERSITY PAPERS: CLICK HERE
For More Question paper on CSE - CLICK HERE
PART A — (10 × 2 = 20 marks)
1. What is loop unrolling? and what are its advantages?
2. Differentiate between static and dynamic branch prediction approaches.
3. What is fine-grained multithreading and what is the advantage and disadvantages of fine-grained multithreading?
4. What a VLIW processor?
5. What is sequential consistency?
6. State the advantages of threading.
7. Differentiate between write-through cache and snoopy cache.
8. Compare SDRAM with DRAM.
9. What is multi–core processor and what are the application areas of multi-core processors?
10. What is a Cell Processor?
PART B — (5 × 16 = 80 marks)
11. (a) Briefly describe any techniques to reduce the control hazard stalls. (16)
Or
(b) (i) Discuss about any two compiler techniques for exposing ILP in detail. (8)
(ii) Explain how ILP is achieved using dynamic scheduling. (8)
12. (a) (i) Describe the architectural features of IA 64 Processors in detail. (10)
(ii) Explain the architecture of a typical VLIW processor in detail. (6)
Or
(b) (i) Describe the architectural features of Itanium Processor. (10)
(ii) Explain how instruction level parallelism is achieved in EPIC processor. (6)
13. (a) (i) Describe the basic structure of a centralized shared-memory multiprocessor in detail. (6)
(ii) Describe the implementation of directory-based cache coherence protocol. (10)
Or
(b) (i) What are the advantages and disadvantages of distributed-memory Multiprocessors? Describe the basic structure of a distributedmemory multiprocessor in detail. (8)
(ii) Describe sequential and relaxed consistency model. (8)
14. (a) (i) With suitable diagram, explain how virtual address is mapped to L2 cache address. (10)
(ii) Discuss about the steps to be followed in designing I/O system. (6)
Or
(b) Describe the optimizations techniques used in compilers to reduce cache miss rate. (16)
15. (a) (i) Describe the features of SUN CMP architecture in detail. (6)
(ii) What are Multi Core processors? Explain how a multi core processors works. (10)
Or
(b) (i) Discuss about the SMT kernel structure in detail. (8)
(ii) Describe the architecture of the IBM Cell Processor in detail. (8)
0 Comments