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B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Sixth Semester
Computer Science and Engineering
CS 2354 — ADVANCED COMPUTER ARCHITECTURE
(Regulation 2008)
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PART A — (10 × 2 = 20 marks)
1. What is instruction level parallelism?
2. What are the advantages of loop unrolling?
3. What are the limitations of VLIW?
4. What is the use of branch-target buffer?
5. Distinguish between shared memory multiprocessor and message-passing multiprocessor.
6. Differentiate multi-threading computers from multiprocessor systems
7. Define the terms cache miss and cache hit.
8. What is RAID?
9. What is a multi-core processor?
10. What is a cell processor?
PART B — (5 × 16 = 80 marks)
11. (a) (i) Explain the data and name dependencies with suitable example. (10)
(ii) Discuss about the benefits and limitations of static branch prediction and dynamic branch prediction (6)
Or
(b) Briefly explain how to overcome data hazards with dynamic scheduling using Tomasulas approach.(16)
12. (a) (i) Describe the architecture of Itanium processor with the help of a block diagram. (8)
(ii) Explain how ILP is achieved in EPIC processors (8)
Or
(b) (i) Describe the architectural features of IA64 processor in detail.(8)
(ii) What are the advantages and disadvantages of software-based and hardware-based speculation mechanism? (8)
13. (a) (i) Briefly compare instruction level parallelism with thread-level parallelism. (8)
(ii) Explain the basic architecture of a distributed memory multiprocessor system. (8)
Or
(b) (i) Explain various memory consistency models in detail. (10)
(ii) What is multithreading and what are the advantages of multithreading? (6)
14. (a) What is meant by cache coherence problem? Describe various protocols for cache coherence.(16)
Or
(b) Briefly explain various I/O performance measures. (16)
15. (a) (i) Describe the architecture of typical CMT processor. (8)
(ii) Discuss the design issues for simultaneous multi-threading. (8)
Or
(b) (i) Explain the architectural features of IBM cell processor in detail. (10)
(ii) Briefly compare SMT and CMP architectures. (6)
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